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Espressif Systems /ESP32-P4 /LEDC /TIMER3_CONF

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Interpret as TIMER3_CONF

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0TIMER_DUTY_RES 0CLK_DIV_TIMER0 (TIMER_PAUSE)TIMER_PAUSE 0 (TIMER_RST)TIMER_RST 0 (TICK_SEL_TIMER)TICK_SEL_TIMER 0 (TIMER_PARA_UP)TIMER_PARA_UP

Description

Timer 3 configuration register

Fields

TIMER_DUTY_RES

Configures the range of the counter in timer %s.
CLK_DIV_TIMER

Configures the divisor for the divider in timer %s.The least significant eight bits represent the fractional part.
TIMER_PAUSE

Configures whether or not to pause the counter in timer %s.\0: Normal\1: Pause
TIMER_RST

Configures whether or not to reset timer %s. The counter will show 0 after reset.\0: Not reset\1: Reset
TICK_SEL_TIMER

Configures which clock is timer %s selected. Unused.
TIMER_PARA_UP

Configures whether or not to update LEDC_CLK_DIV_TIMER%s and LEDC_TIMER%s_DUTY_RES.\0: Invalid. No effect\1: Update

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data